Design of a Low Voltage-Low Power 3.1–10.6 GHz UWB RF Front-End in a CMOS 65 nm Technology

In this brief, the design of a 3.1 to 10.6 GHz ultra wideband (UWB) RF front-end (RFFE) is presented. It employs a novel low noise common gate amplifier combined with a noise canceling circuit, that provides wideband input matching, high voltage gain and low noise figure in the whole band of operation. It also adopts a passive single balanced direct conversion mixer with a custom designed balun at its local oscillator (LO) input. The RFFE achieves 20.6 dB of voltage gain and it has adequately flat frequency response. Its noise figure is 3-3.8 dB and the CP1 at the input is -19.7 dBm. The circuit consumes only 10.8 mW from a 1.2 V supply and it was designed in IBM´s CMOS 65 nm process.