Title :
Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
Author :
Hsiao, Shen-Fu ; Jiang, Ming-Roun ; Yeh, Jia-Sien
Author_Institution :
Inst. of Comput. & Inf. Eng., Nat. Sun Yat-Sen Univ., Taiwan
fDate :
2/19/1998 12:00:00 AM
Abstract :
A 3-2 counter and a 4-2 compressor are the basic components in the partial product summation tree of a parallel array multiplier. A new high-speed and low power design of these components is presented. Owing to the reduction of the internal load capacitance, the counter and compressor have better speed and power performance than other recently proposed approaches
Keywords :
adders; capacitance; counting circuits; data compression; multiplying circuits; high-speed circuits; internal load capacitance; low-power 3-2 counter; low-power 4-2 compressor; multipliers; parallel array multiplier; partial product summation tree; power performance;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980306
