DocumentCode
1379544
Title
Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
Author
Hsiao, Shen-Fu ; Jiang, Ming-Roun ; Yeh, Jia-Sien
Author_Institution
Inst. of Comput. & Inf. Eng., Nat. Sun Yat-Sen Univ., Taiwan
Volume
34
Issue
4
fYear
1998
fDate
2/19/1998 12:00:00 AM
Firstpage
341
Lastpage
343
Abstract
A 3-2 counter and a 4-2 compressor are the basic components in the partial product summation tree of a parallel array multiplier. A new high-speed and low power design of these components is presented. Owing to the reduction of the internal load capacitance, the counter and compressor have better speed and power performance than other recently proposed approaches
Keywords
adders; capacitance; counting circuits; data compression; multiplying circuits; high-speed circuits; internal load capacitance; low-power 3-2 counter; low-power 4-2 compressor; multipliers; parallel array multiplier; partial product summation tree; power performance;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19980306
Filename
675681
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