DocumentCode
1380320
Title
Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility
Author
Conte, Thomas M. ; Sathaye, Sumedh
Author_Institution
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Volume
49
Issue
8
fYear
2000
fDate
8/1/2000 12:00:00 AM
Firstpage
814
Lastpage
825
Abstract
The object-code compatibility problem in VLIW architectures stems from their statically scheduled nature. Dynamic rescheduling (DR) is a technique to solve the compatibility problem in VLIWs. DR reschedules program code pages at first-time page faults, i.e., when the code pages are accessed for the first time during execution. Treating a page of code as the unit of rescheduling makes it susceptible to the hazards of changes in the page size during the process of rescheduling. This paper shows that the changes in the page size are only due to insertion and/or deletion of NOPs in the code. Further, it presents an ISA encoding, called list encoding, which does not require explicit encoding of the NOPs in the code. Algorithms to perform rescheduling on acyclic code and cyclic code are presented, followed by the discussion of the property of rescheduling-size invariance (RSI) satisfied by list encoding
Keywords
cyclic codes; encoding; parallel architectures; processor scheduling; ISA encoding; VLIW architectures; acyclic code; cyclic code; dynamic rescheduling-based VLIW cross-generation compatibility; list encoding; object-code compatibility problem; program code pages; rescheduling size invariance; Delay; Dynamic scheduling; Encoding; Hardware; Hazards; Helium; Instruction sets; Processor scheduling; Runtime; VLIW;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.868027
Filename
868027
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