SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application

Author

Greshishchev, Yuriy M. ; Schvan, Peter

Author_Institution

Nortel Networks, Ottawa, Ont., Canada

Volume

35

Issue

9

fYear

2000

Firstpage

1353

Lastpage

1359

Abstract

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV/sub pp/ at a bit error rate (BER)=10/sup -9/. The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply.

Keywords

BIMOS integrated circuits; Ge-Si alloys; SONET; data communication equipment; digital communication; high-speed integrated circuits; mixed analog-digital integrated circuits; optical receivers; phase locked loops; semiconductor materials; synchronization; timing jitter; -5 V; 1.5 W; 10 Gbit/s; 9.529 to 13.25 Gbit/s; ASIC; BER; CDR circuit; Hogge phase detector; LC-tank VCO; PLL equivalent model; SONET application; SONET jitter requirements; SiGe; SiGe HBT bipolar process; SiGe clock/data recovery IC; bit error rate; clock jitter; clock recovery IC; data recovery IC; design method; linear-type PLL; pMOS devices; phase-locked loop; single-edge version; tri-state charge pump; voltage-controlled oscillator; Charge pumps; Clocks; Detectors; Germanium silicon alloys; Integrated circuit technology; Jitter; Phase detection; Phase locked loops; Silicon germanium; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.868047

Filename

868047