Systematic Analysis of Interleaved Digital-to-Analog Converters

Author

Balasubramanian, S. ; Creech, G. ; Wilson, J. ; Yoder, S.M. ; McCue, J.J. ; Verhelst, M. ; Khalil, W.

Author_Institution

Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH, USA

Volume

58

Issue

12

fYear

2011

Firstpage

882

Lastpage

886

Abstract

A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising N -parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined.

Keywords

digital-analogue conversion; parallel architectures; replica techniques; RF-DAC architecture; bandwidth enhancement; clock and hold interleaving structure; different path mismatch effect; image replica cancellation; interleaved digital-to-analog converter; mathematical model; n-parallel DAC; resolution enhancement; return-to-zero variant; DC-AC power converters; Digital-analog conversion; Interleaved codes; Mathematical model; DDRF-DAC; digital-to-analog converters (DACs); interleaving; reconstruction;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2011.2172526

Filename

6085601