Optimal state assignment technique for partial scan designs

The state assignment of a finite state machine greatly affects the delay, area and testability of sequential circuits. To reduce the length and number of feedback cycles, a new state assignment technique based on m-block partitioning is introduced. Following the completion of the proposed state assignment and logic synthesis stage, partial scan design is performed to choose the minimal number of scan flip-flops. Experimental results show that a drastic improvement in testability can be realised while maintaining a low area and delay overhead