DocumentCode
1381057
Title
Frame synchronisation circuit for high-transmission-rate CMOS systems
Author
de Vasconcelos, E. ; Aguiar, R.L.
Author_Institution
Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
Volume
36
Issue
18
fYear
2000
fDate
8/31/2000 12:00:00 AM
Firstpage
1592
Lastpage
1593
Abstract
The authors present a technique for frame synchronisation in high-speed telecommunications systems. The described structure allows frame synchronisation to be performed independently from the technology inherent delays. The principle has been tested in a 0.8 μm CMOS SDH/STM-4 (622.08 Mbit/s) system and was able to generate the synchronisation pulse with the necessary accuracy
Keywords
CMOS digital integrated circuits; data communication equipment; digital communication; synchronisation; 0.8 micron; 622.08 Mbit/s; SDH/STM-4 system; frame synchronisation circuit; high-speed telecommunications systems; high-transmission-rate CMOS systems; synchronisation pulse generation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20001087
Filename
868133
Link To Document