• DocumentCode
    1381350
  • Title

    Circuit improvements for high-speed domino logic: for the Manchester carry chain

  • Author

    Blair, G.M.

  • Author_Institution
    Dept. of Electr. Eng., Edinburgh Univ., UK
  • Volume
    34
  • Issue
    3
  • fYear
    1998
  • fDate
    2/5/1998 12:00:00 AM
  • Firstpage
    247
  • Lastpage
    248
  • Abstract
    Circuit techniques are introduced to reduce the delay of pass-transistor chains within the domino-logic implementation of a Manchester carry chain: the quadratic dependency on the number of bits is made linear without increasing transistor sizes
  • Keywords
    CMOS logic circuits; adders; carry logic; delays; logic design; Manchester carry chain; delay reduction; high-speed domino logic; pass-transistor chains;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980236
  • Filename
    677336
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1381350