Title :
A CMOS buffer without short-circuit power consumption
Author_Institution :
Integrated Syst. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
fDate :
9/1/2000 12:00:00 AM
Abstract :
A new CMOS buffer without short-circuit power consumption is proposed. The gate-driving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption, The HSPICE simulation results verified the operation of the proposed buffer and showed the power-delay product is about 15% smaller than conventional tapered CMOS buffer
Keywords :
CMOS logic circuits; SPICE; buffer circuits; circuit feedback; circuit simulation; logic simulation; CMOS buffer; HSPICE simulation results; gate-driving signal; output pull-down transistor; output pull-up transistor; power-delay product; tri-state output; CMOS logic circuits; Driver circuits; Energy consumption; Inverters; Nonlinear filters; Signal processing; Signal processing algorithms; Speech processing; Timing; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
