DocumentCode
1382111
Title
Development of virtual reliability methodology for area-array devices used in implantable and automotive applications
Author
Sitaraman, Suresh K. ; Raghunathan, Rajiv ; Hanna, Carlton Eissey
Author_Institution
George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Volume
23
Issue
3
fYear
2000
fDate
9/1/2000 12:00:00 AM
Firstpage
452
Lastpage
461
Abstract
The number of thermal cycles, the temperature range, and the time of dwell used for qualifying a microelectronic package should be based on the type of application the package is intended for. However, in the absence of specific guidelines, the industrial practice is to subject the devices to military-standard qualification tests without adequate consideration for the application the devices are intended for. This work aims at developing temperature cycling guidelines for packages used in implantable medical devices and automotive applications taking into consideration the thermal history associated with the field conditions. Numerical models have been developed that take the time- and temperature-dependent behavior of the solder joints and the viscoelastic behavior of the underfill besides the temperature-dependent orthotropic properties of the substrate for a flip-chip on board (FCOB) assembly and a flip chip chip-scale package (FCCSP) on organic board assembly. The models account for solder reflow process, underfill cure process, and burn-in testing of the devices. Qualification temperature cycling guidelines have been developed for implantable devices based on the information collected in terms of shipping, EM sterilization, and implantation temperature profiles, and for the automotive devices based on the representative field conditions
Keywords
chip scale packaging; chip-on-board packaging; encapsulation; flip-chip devices; integrated circuit packaging; integrated circuit reliability; reflow soldering; viscoelasticity; EM sterilization; area-array devices; automotive applications; burn-in testing; dwell; field conditions; flip chip chip-scale package; flip-chip on board; implantable applications; implantation temperature profiles; microelectronic package; military-standard qualification tests; solder joints; solder reflow process; temperature cycling guidelines; temperature range; temperature-dependent behavior; temperature-dependent orthotropic properties; thermal cycles; thermal history; time-dependent behavior; underfill; underfill cure process; virtual reliability methodology; viscoelastic behavior; Assembly; Automotive applications; Defense industry; Guidelines; Implantable biomedical devices; Microelectronics; Packaging; Qualifications; Temperature distribution; Testing;
fLanguage
English
Journal_Title
Components and Packaging Technologies, IEEE Transactions on
Publisher
ieee
ISSN
1521-3331
Type
jour
DOI
10.1109/6144.868844
Filename
868844
Link To Document