DocumentCode :
138287
Title :
Fabrication of strained Ge on insulator via room temperature wafer bonding
Author :
Asadollahi, A. ; Radamson, H. ; Zabel, Thomas ; Hellstrom, Per-Erik ; Ostling, Mikael
Author_Institution :
Sch. of ICT, KTH R. Inst. of Technol., Kista, Sweden
fYear :
2014
fDate :
7-9 April 2014
Firstpage :
81
Lastpage :
84
Abstract :
This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).
Keywords :
Ge-Si alloys; chemical vapour deposition; etching; semiconductor growth; semiconductor materials; silicon-on-insulator; wafer bonding; GeOI fabrication process; RPCVD; Si0.66Ge0.34; etch-back techniques; partially relaxed layer; reduced pressure chemical vapor deposition; room temperature wafer bonding; strained germanium on insulator fabrication; temperature 293 K to 298 K; Bonding; Rough surfaces; Silicon; Substrates; Surface roughness; Surface treatment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Ultimate Integration on Silicon (ULIS), 2014 15th International Conference on
Conference_Location :
Stockholm
Type :
conf
DOI :
10.1109/ULIS.2014.6813911
Filename :
6813911
Link To Document :
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