Mismatch trends in 20nm gate-last bulk CMOS technology

In this work Vt and β mismatch for the 20 nm Gate-last bulk CMOS technology are investigated for the first time. Our results indicate that the 20 nm Gate-last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28 nm Gate-first counterpart. Furthermore, the evolution of the Vt and β mismatch parameters, iA_ΔVt and iA_Δβ/β, is analyzed as a function of EOT (Tox) from the 90 nm technology node down to the 20 nm technology node. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot iA_ΔVt vs EOT is observed from the 28 nm Gate-first technology, with such offset approaching zero for the 20 nm Gate-last technology node. This indicates evidence of a huge decrease in the mismatch contribution of the gate material.