Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics

Author

Sun, Jie J. ; Osburn, Carlton M.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

Volume

45

Issue

6

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

1377

Lastpage

1380

Abstract

Deep submicron elevated source/drain (S/D) MOSFET´s with epi facets, without facets, and with a second sidewall spacer covering the facets were studied using two-dimensional (2-D) process and device simulations. A slight degradation of drain-induced-barrier-lowering ΔV_t (DIBL) has been projected due to the locally deeper junction beneath the epi facets. The locally deeper junction also shortens the S/D extension length if the spacer thickness is kept the same. The shorter extension in turn leads to a smaller parasitic resistance and therefore a higher device drive current. Gate-to-drain capacitance of the elevated S/D MOSFET is decreased as a result of faceting because of the reduced overlap area

Keywords

MOS integrated circuits; MOSFET; capacitance; semiconductor device models; semiconductor process modelling; 2D process simulations; S/D extension length; deep submicron elevated source/drain MOSFET characteristics; device drive current; device simulations; drain-induced-barrier-lowering; epi facets; gate-to-drain capacitance; locally deeper junction; overlap area; parasitic resistance; sidewall spacer; CMOS technology; Degradation; Epitaxial growth; MOSFET circuits; Parasitic capacitance; Process design; Substrates; Sun; Transconductance; Two dimensional displays;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.678583

Filename

678583