Design of a scalable pipelined RAM system

Author

Jeong, Gab Joong ; Lee, Moon Key

Author_Institution

Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea

Volume

33

Issue

6

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

910

Lastpage

914

Abstract

This paper describes a scalable pipelined RAM system (SPRAMS) for packet switching. The SPRAMS consists of a two-dimensional array of small memory blocks which are fully pipelined and communicate with adjacent blocks in three directions. The maximum delay of a small memory block becomes the cycle time of the chip. The array configuration is scalable for large memory size without the cycle time variation. It has an initial latency of N+3 cycles with an N×N array configuration. We have designed an experimental 200 MHz 4 kbit static RAM chip with the 4×4 array configuration of 256 bit SRAM blocks. It was fabricated in 0.8 μm single-poly double-metal CMOS technology. Experimental results describe the advantages of SPRAMS

Keywords

CMOS memory circuits; SRAM chips; asynchronous transfer mode; memory architecture; packet switching; pipeline processing; random-access storage; 0.8 micron; 200 MHz; 256 bit; 4 kbit; ATM switch system application; SRAM blocks; memory blocks; packet switching; scalable pipelined RAM system; single-poly double-metal CMOS technology; two-dimensional array; Asynchronous transfer mode; Bandwidth; CMOS technology; Decoding; Delay effects; Packet switching; Random access memory; Read-write memory; Scalability; Switches;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.678657

Filename

678657