DocumentCode :
1384060
Title :
The Transmogrifier-2: a 1 million gate rapid-prototyping system
Author :
Lewis, David M. ; Galloway, David R. ; Van Ierssel, Marcus ; Rose, Jonathan ; Chow, Paul
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Volume :
6
Issue :
2
fYear :
1998
fDate :
6/1/1998 12:00:00 AM
Firstpage :
188
Lastpage :
198
Abstract :
This paper describes the Transmogrifier-2 (TM-2), a second-generation multifield programmable gate array (FPGA) rapid-prototyping system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGA´s, four I-Cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a nonuniform partial crossbar, that provides a constant delay between any two FPGA´s in the system. The TM-2 architecture is modular and scalable, meaning that systems of various sizes can be constructed from copies of the same board, while maintaining routability and the constant delay feature. Other features include a system-level programmable clock that allows single-cycle access to off-chip memory, and programmable clock waveforms with edge resolution of 10 ns. The first Transmogrifier-2 boards have been manufactured and are functional. They have recently been used successfully in some simple graphics acceleration applications.
Keywords :
VLSI; circuit layout CAD; clocks; field programmable gate arrays; logic CAD; network routing; software prototyping; 8 Mbyte; Altera 10K50 FPGA; I-Cube interconnect chips; TM-2 architecture; Transmogrifier-2; constant delay; edge resolution; graphics acceleration applications; inter-FPGA routing architecture; interconnect structure; nonuniform partial crossbar; programmable clock waveforms; rapid-prototyping system; routability; second-generation multifield programmable gate array; single-cycle access; system-level programmable clock; Application software; Clocks; Computer architecture; Delay; Emulation; Engines; Field programmable gate arrays; Integrated circuit interconnections; Prototypes; Routing;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.678867
Filename :
678867
Link To Document :
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