Low-power pulse-triggered flip-flop design using gated pull-up control scheme

A new implicit type pulse triggered flip-flop design aimed at solving a common transistor stacking problem is presented. A pull-up transistor gating scheme is devised to avoid a bulky discharging path causing excessive power consumption. Via a bootstrap technique, the required gating pulse signal is obtained free from a modified delay inverter design. Circuit analyses and post-layout simulations are provided to prove the superiority of the design in terms of layout area and power-delay product.