DocumentCode :
1384095
Title :
Some experiments about wave pipelining on FPGA´s
Author :
Boemo, Eduardo I. ; López-Buedo, Sergio ; Meneses, Juan M.
Author_Institution :
Lab. de Microelectron., Univ. Autonoma de Madrid, Spain
Volume :
6
Issue :
2
fYear :
1998
fDate :
6/1/1998 12:00:00 AM
Firstpage :
232
Lastpage :
237
Abstract :
Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and buffers with data-independent delays and the knowledge of the interconnection delays. These two features are present in several SRAM-based field programmable gate arrays (FPGA´s): look-up tables (LUT´s) allow the designer to mask the delay of different gates and combinational functions, and the timing characteristics of each wire segment are a priori known. This work describes a set of experiments about wave pipelining on FPGA´s. The results show that a 13-LUT logic depth circuit mapped on an XC4005PC84-6 runs as high as 85 MHz (single phase clocking) or 80 MHz (intentionally skewed clocking), exhibiting a latency of 95 ns. This high throughput/latency ratio is unattainable using classic pipelining.
Keywords :
delays; field programmable gate arrays; logic design; pipeline processing; table lookup; timing; 13-LUT logic depth circuit; FPGA design; SRAM-based FPGAs; XC4005PC84-6; data-independent delays; field programmable gate arrays; high throughput/latency ratio; intentionally skewed clocking; interconnection delays; lookup tables; single phase clocking; timing characteristics; wave pipelining; Clocks; Energy consumption; Field programmable gate arrays; Integrated circuit interconnections; Pipeline processing; Programmable logic arrays; Propagation delay; Table lookup; Timing; Wire;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.678876
Filename :
678876
Link To Document :
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