Off-track testing to evaluate ESD damage to MR heads

Several magnetoresistive heads (850 Mbits/in² areal density) were electrically characterized on a spin stand, as-received and following controlled “zapping” simulating ESD events which may occur during manufacturing processes at the head-gimbal (HGA) or head-stack (HSA) level. The ESD “zap” was delivered by the discharge of a 150 pF capacitor across the MR head in series with a 150 ohm resistor. Offtrack read capability and peak-to-peak amplitude of the heads degraded after exposure to 10 discharges for charging voltages as low as 20 volts, even though DC resistance remained unchanged. We concluded that the measurement of DC resistance is inadequate to ensure ESD control in a manufacturing process. We also concluded that a 20 volt maximum on the factory floor is a good starting point for ESD control for this generation of SAL-biased MR heads