Modulated integral control technique for compensating switch delays and nonideal DC buses in voltage-source inverters

Standard pulsewidth modulation (PWM) techniques assume a ripple-free DC-link voltage at the inverter input terminals and ideal switches. Most techniques proposed in the literature to compensate the nonideal characteristics require additional and complex circuitry. This paper proposes and analyzes a simple method of generating PWM switching patterns which ensures a high-quality output voltage and inherently compensates for a nonideal DC bus and switching delays. The method is based on maintaining a sinusoidal volt-second distribution at the inverter output by sensing the output voltage and generating the gating pattern online. The principles of operation are explained, and a design procedure is presented. Simulation results illustrating the features of the proposed modulator are verified experimentally on a 3 kVA prototype unit