DocumentCode :
1384943
Title :
A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel 
ADC Architecture
Author :
Chae, Youngcheol ; Cheon, Jimin ; Lim, Seunghyun ; Kwon, Minho ; Yoo, Kwisung ; Jung, Wunki ; Lee, Dong-Hun ; Ham, Seogheon ; Han, Gunhee
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Volume :
46
Issue :
1
fYear :
2011
Firstpage :
236
Lastpage :
247
Abstract :
This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-μm CMOS process. Measurement results show a RN of 2.4 erms- and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e-·nJ.
Keywords :
CMOS image sensors; analogue-digital conversion; delta-sigma modulation; filters; random noise; CMOS image sensor; CMOS process; column-parallel ΔΣ ADC architecture; column-parallel delta-sigma ADC architecture; compact decimation filter; conversion speed; energy efficiency; inverter-based ΔΣ modulator; power 180 mW; power consumption; random noise; second-order ΔΣ ADC; size 0.13 mum; CMOS image sensors; Capacitors; Clocks; Inverters; Modulation; Noise; Pixel; CMOS image sensor; column-parallel delta-sigma $(Delta Sigma)$ $Delta Sigma$ ADC;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2010.2085910
Filename :
5641589
Link To Document :
