Optimizing Power of Switched Capacitor Integrators in Sigma-Delta Modulators

This work describes a method that computationally determines the minimum required power and sampling capacitance for a switched capacitor integrator in a sigma delta modulator, given the modulator architecture, coefficients, and desired SNDR target. The design space is quickly explored with discrete time simulations that model the finite gain, settling dynamics, and thermal noise of the integrators. Insight gained from simulation can help the designer choose the number of quantizer levels in a multi-bit architecture or help him or her decide if a higher performance op amp and/or different modulator architecture is needed to attain the required power performance.