DocumentCode
1386341
Title
A low-power PLA for a signal processor
Author
Linz, Alfredo R.
Author_Institution
Adv. Micro Devices Inc., Austin, TX, USA
Volume
26
Issue
2
fYear
1991
fDate
2/1/1991 12:00:00 AM
Firstpage
107
Lastpage
115
Abstract
A standard fast programmable logic array (PLA) structure is discussed, with emphasis on its power consumption drawbacks. An exploration of alternatives to this structure leads to a presentation of the architecture and design of a low-power PLA structure used in a digital signal processing (DSP) environment. This PLA achieves low power consumption by a combination of pipelining, use of a NAND-OR configuration, and a simplified addressing scheme. Experimental results for the temperature range of 0 to 70°C indicate that the circuit works as expected in a range extending to at least 3.5 V
Keywords
computerised signal processing; logic arrays; logic design; pipeline processing; 0 to 70 degC; 3.5 V; DSP environment; NAND-OR configuration; addressing scheme; digital signal processing; low-power PLA; pipelining; power consumption; programmable logic array; signal processor; Algorithms; CMOS technology; Codecs; Digital signal processing; Energy consumption; Filters; Power dissipation; Programmable logic arrays; Signal design; Signal processing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.68124
Filename
68124
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