Design of fast high-radix SRT dividers and their VLSI implementation

Division accounts for a significant fraction of the total arithmetic operations, and most implementations for the division are based on the SRT algorithm that uses a recurrence producing one quotient digit for each step. The complexity of the quotient-digit selection process can be simplified significantly by using a look-up table, referred to as the quotient-digit selection table (QST). However, the table size of the conventional QST approach increases unmanageably as the radix increases. For fast high-radix applications, the study proposes an alternative approach which determines the quotient digit using two much smaller tables instead of a huge table for the conventional approach. The proposed process is comprised of two major steps: estimation of quotient digit and correction of the estimated quotient digit and updating the partial remainder. Results show that the table size is reduced significantly. Further, an estimation limit is introduced to keep the table size reasonably small when the radix increases. Thus the proposed approach can be well-suited for high-radix implementation