Design of a unified arithmetic processor based on redundant constant-factor CORDIC with merged scaling operation

Author

Hsiao, S.-F. ; Lau, C.-Y.

Author_Institution

Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

147

Issue

4

fYear

2000

fDate

7/1/2000 12:00:00 AM

Firstpage

297

Lastpage

303

Abstract

An arithmetic processor is designed based on redundant constant-factor implementation of the coordinate rotation digital computer (CORDIC) algorithm with three different modes: circular, hyperbolic and linear. Both CORDIC types (angle calculation and vector rotation) are considered in this unified processor that is capable of computing a wide variety of arithmetic and elementary functions including: multiplication, division, some common trigonometric functions, natural logarithms, square roots, vector norm and phase. Furthermore, by merging the scaling operation with the regular CORDIC iterations, the processor based on folded (iterative) CORDIC architecture reduces by about 1/4 the total number of iterations in one complete CORDIC operation

Keywords

digital arithmetic; signal processing; angle calculation; coordinate rotation digital computer algorithm; merged scaling operation; natural logarithms; redundant constant-factor CORDIC; redundant constant-factor implementation; square roots; trigonometric functions; unified arithmetic processor; vector norm; vector rotation;

fLanguage

English

Journal_Title

Computers and Digital Techniques, IEE Proceedings -

Publisher

iet

ISSN

1350-2387

Type

jour

DOI

10.1049/ip-cdt:20000533

Filename

870985