DocumentCode
1386513
Title
A Charge Trap Folded nand Flash Memory Device With Band-Gap-Engineered Storage Node
Author
Cho, Seongjae ; Shim, Won Bo ; Kim, Yoon ; Yun, Jang-Gn ; Lee, Jong Duk ; Shin, Hyungcheol ; Lee, Jong-Ho ; Park, Byung-Gook
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
Volume
58
Issue
2
fYear
2011
Firstpage
288
Lastpage
295
Abstract
A charge trap folded NAND (FNAND) Flash memory device with band-gap-engineered (BE) storage node is proposed. Because of the compact cell layout without junction contacts, a NAND Flash memory is the most suitable memory medium for electronic appliances. Two memory cells are put together to have a common vertical channel, which enables one to achieve a theoretical near-30-nm technology. The resulting array is made by folding the conventional 2-D Flash memory and is called FNAND. The memory storage node uses a BE stack structure, where the oxide-nitride-oxide multilayers replace the tunnel oxide. The fin structures for both wordline and bitline have been formed by sidewall spacer patterning, instead of photolithography. The fabrication processes for SONONOS NAND Flash memory having independent double gates are explained. Electrical characteristics regarding memory operations under paired cell interference are analyzed.
Keywords
NAND circuits; flash memories; logic gates; SONONOS NAND flash memory; band gap engineered storage node; charge trap; compact cell layout; double gates; electronic appliances; folded NAND flash memory device; memory storage node; oxide-nitride-oxide multilayers; sidewall spacer patterning; vertical channel; Arrays; Flash memory; Junctions; Lithography; Logic gates; Performance evaluation; Silicon; Band-gap engineering; charge trap; double gate; flash memory; folded nand (F nand); paired cell interference (PCI); sidewall spacer patterning;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2010.2090420
Filename
5643136
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