Title :
A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances
Author :
Jui-Jen Wu ; Meng-Fan Chang ; Shau-Wei Lu ; Lo, Raymond ; Li, Qifeng
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Eight-transistor (8T) dual-port static random access memory (DP-SRAM) suffers from read and write disturbances at low voltages when both ports are accessed simultaneously, and write disturbance dominates the VDDmin in high-speed applications. This brief proposes a write-assist 8T (WA8T) cell to suppress the write disturbance for DP-SRAM to achieve a lower VDDmin with low area overhead and power consumption. We fabricated a 1-Mbit DP-SRAM with WA8T testchip using a 40-nm CMOS process. The proposed WA8T device achieved a 120-mV improvement in VDDmin with less than 1% area overhead.
Keywords :
CMOS digital integrated circuits; SRAM chips; 8T DP-SRAM; CMOS process; WA8T testchip; eight-transistor dual-port static random access memory; high-speed applications; low area overhead; power consumption; read disturbances; size 40 nm; size 45 nm; voltage 120 mV; write disturbances; write-assist 8T cell; write-assist cells utilization; Inverters; Layout; Power demand; Random access memory; Solid state circuits; Timing; Very large scale integration; Dual-port static random access memory (DP-SRAM); low supply voltage;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2012.2228398
