Performance analysis of multistage interconnection networks with hierarchical requesting model

Analyzes the performance of the multistage interconnection networks (MINs) for interconnecting N processors or N processors to N commonly shared memory modules in a multiprocessor system. A general model, called hierarchical requesting model, has been proposed. The performance of the MINs with respect to their memory bandwidth is analyzed and is compared to that of a crossbar under the proposed model. Based on the analytical results, the authors present a task allocation strategy to increase the memory bandwidth of the MINs