A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current

Author

Kawaguchi, Hiroshi ; Nose, Koichi ; Sakurai, Takayasu

Author_Institution

Dept. of Ind. Sci., Tokyo Univ., Japan

Volume

35

Issue

10

fYear

2000

Firstpage

1498

Lastpage

1501

Abstract

A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level.

Keywords

CMOS logic circuits; VLSI; high-speed integrated circuits; integrated circuit reliability; leakage currents; low-power electronics; 0.1 to 0.2 V; 0.5 V; SCCMOS; VLSIs; active mode; current level; high-speed operation; leakage current; low-threshold voltage; picoampere stand-by current; stand-by mode; super cut-off CMOS; Batteries; CMOS logic circuits; Delay; Leakage current; Libraries; Logic circuits; Logic gates; MOS devices; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.871328

Filename

871328