Title :
Optimization of NLDMOS structure for higher breakdown voltage and lower On-Resistance
Author :
Hema, E.P. ; Sheu, G. ; Aryadeep, M. ; Kurniawan, Erry Dwi ; Yang, S.M. ; Chen, P.A.
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan
Abstract :
In this work, high voltage NLDMOS performance in terms of high blocking voltage and On-Resistance have been investigated. In order to obtain the optimum electrical performance several key factors have been optimized such as linearity of HVNW profile, drift length and source field plate. Linear HVNW profile is obtained by linearity of HVNW mask. NLDMOS having blocking voltage of 100 V-300 V and lower On-resistance is developed based on 0.35um BCD Technology with less manufacturing cost. It is investigated that NLDMOS has poor performance over blocking voltage of 300V.
Keywords :
MOSFET; semiconductor device breakdown; BCD technology; HVNW mask; NLDMOS structure optimization; drift length; high blocking voltage; high voltage NLDMOS performance; higher breakdown voltage; linear HVNW profile; lower on-resistance; optimum electrical performance; size 0.35 mum; source field plate; voltage 100 V to 300 V; Asia; Breakdown voltage; Computer science; Educational institutions; Impact ionization; Logic gates; Optimization;
Conference_Titel :
Power Engineering and Optimization Conference (PEOCO), 2014 IEEE 8th International
Conference_Location :
Langkawi
Print_ISBN :
978-1-4799-2421-9
DOI :
10.1109/PEOCO.2014.6814416
