A study of interstitial effect on UMOS performance

Author

Hema, E.P. ; Gene Sheu ; Aryadeep, M. ; Yang, S.M.

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan

fYear

2014

fDate

24-25 March 2014

Firstpage

178

Lastpage

181

Abstract

Threshold voltage shift is a major problem for UMOS device. This study explains how device performance can be affected by silicon defects (interstitial and Vacancy). Interstitial may be induced by epitaxy process or trench process. Interstitial enhances the dopant diffusion. In TCAD simulation interstitial distribution is different for different diffusion model and shows shift in the threshold voltage for different interstitial distribution.

Keywords

MOSFET; electronic engineering computing; elemental semiconductors; epitaxial growth; interstitials; isolation technology; semiconductor doping; technology CAD (electronics); TCAD simulation interstitial distribution; U shaped gate MOSFET; UMOS device; UMOS performance; diffusion model; dopant diffusion; epitaxy process; interstitial effect; silicon defects; threshold voltage shift; trench process; vacancy; Asia; Educational institutions; Logic gates; Mathematical model; Semiconductor device modeling; Semiconductor process modeling; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Engineering and Optimization Conference (PEOCO), 2014 IEEE 8th International

Conference_Location

Langkawi

Print_ISBN

978-1-4799-2421-9

Type

conf

DOI

10.1109/PEOCO.2014.6814421

Filename

6814421