Chip-scale packaging

Author

Thompson, Patrick

Author_Institution

Semicond. Technol. Group, Motorola Inc., Tempe, AZ, USA

Volume

34

Issue

8

fYear

1997

fDate

8/1/1997 12:00:00 AM

Firstpage

36

Lastpage

43

Abstract

Uniting the advantages of bare die and mainstream packaging, these minimal IC supports are racing to the aid of portable yet powerful products. Rigorously defined, the perimeter of such a package is no more than 1.2 times the perimeter of the die it contains, so that few other IC packages are any smaller. This reduction in size is the key driver of the popularity of the approach. But because the term chip-scale has a marketing value, some manufacturers have extended it to cover other sizes, too. Chip-scale packaging technology is still taking its first steps into the marketplace, and issues of standards, design, and reliability remain to be solved. Even so, an infrastructure for the technology is beginning to develop, and its potential market seems to be guaranteed, not least by consumer thirst for portable electronic applications, for which the small, light package is a natural

Keywords

integrated circuit packaging; IC packages; bare die packaging; chip-scale packaging; mainstream packaging; minimal IC supports; portable electronic applications; portable products; reliability; standards; Application software; Chip scale packaging; Costs; Electronics packaging; Lead; Military computing; Packaging machines; Plastic packaging; Protection; Semiconductor device packaging;

fLanguage

English

Journal_Title

Spectrum, IEEE

Publisher

ieee

ISSN

0018-9235

Type

jour

DOI

10.1109/6.609473

Filename

609473