DocumentCode
1389710
Title
The design, analysis and simulation of a fault-tolerant interconnection network supporting the fetch-and-add primitive
Author
Banerjee, Prithu ; Dugar, Abhijeet
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Volume
38
Issue
1
fYear
1989
fDate
1/1/1989 12:00:00 AM
Firstpage
30
Lastpage
46
Abstract
The combining multistage interconnection network uses 4×4 switches as switching elements and introduces an extra stage of such switches and links to create four independent paths between any source-destination pair. Four copies of every message are sent through the network simultaneously. The scheduling discipline, the design of the switching elements to support the discipline, and the theoretical proof of correctness of the design constitute the key contributions of this study. Estimates are provided of various network parameters as a function of the workload, using analytical models and detailed network simulations. It is shown that the proposed design for fault tolerance is more cost-effective than the brute-force technique of having multiple copies of the network
Keywords
fault tolerant computing; multiprocessor interconnection networks; 4×4 switches; analytical models; combining multistage interconnection network; fault-tolerant interconnection network; fetch-and-add primitive; four independent paths; network simulations; omega network; scheduling; Analytical models; Computational modeling; Concurrent computing; Error correction; Fault tolerance; Multiprocessor interconnection networks; Parallel machines; Read-write memory; Scheduling; Switches;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.8728
Filename
8728
Link To Document