Title :
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature
Author :
Takahashi, Ryo ; Takata, Hiroto ; Yasufuku, T. ; Fuketa, Hiroshi ; Takamiya, Makoto ; Nomura, M. ; Shinohara, Hirofumi ; Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan
Abstract :
Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 °C to -40°C, the sigma/average (σ/μ) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σ/μ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.
Keywords :
CMOS logic circuits; delay circuits; logic circuits; logic gates; logic testing; temperature; CMOS test chips; size 40 nm; subthreshold logic circuits; temperature dependence; voltage 0.3 V; within-die random gate delay variations; Delays; Integrated circuit modeling; Logic gates; Low voltage; Semiconductor device measurement; Temperature dependence; Temperature measurement; Voltage measurement; Delay variations; device matrix array (DMA); sub-threshold; temperature;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2012.2231038
