An advanced 0.5- mu m CMOS disposable TiN LDD/salicide spacer process

Author

Pfiester, James R. ; Parrillo, Louis C. ; Woo, Michael ; Kawasaki, Hisao ; Boeck, Bruce ; Travis, Edward O. ; Gunderson, Craig D.

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

11

Issue

7

fYear

1990

fDate

7/1/1990 12:00:00 AM

Firstpage

318

Lastpage

320

Abstract

An advanced 0.5- mu m CMOS technology which features disposable TiN spacers to define both lightly doped drain (LDD) implantation and self-aligned silicided source, drain, and gate regions is discussed. Since the LDD implantation sequences are reversed using the disposable TiN spacers, this process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus N/sup -/ and boron P/sup -/ regions for improved short-channel behavior.<>

Keywords

CMOS integrated circuits; integrated circuit technology; ion implantation; titanium compounds; 0.5 micron; CMOS technology; LDD implantation sequences; disposable TiN spacers; improved short-channel behavior; lightly doped drain; low salicided junction leakage; reduced source/drain lateral diffusion; salicide spacer process; salicided drain region; salicided source region; self-aligned silicided source; shallow doped regions; submicron salicided gate region; Annealing; CMOS process; CMOS technology; Etching; Implants; MOS devices; MOSFET circuits; Space technology; Tin; Titanium;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.56487

Filename

56487