DocumentCode :
1391353
Title :
A Ferroelectric and Charge Hybrid Nonvolatile Memory—Part I: Device Concept and Modeling
Author :
Rajwade, Shantanu R. ; Auluck, Kshitij ; Phelps, Joshua B. ; Lyon, Keith G. ; Shaw, Jonathan T. ; Kan, Edwin Chihchuan
Author_Institution :
Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA
Volume :
59
Issue :
2
fYear :
2012
Firstpage :
441
Lastpage :
449
Abstract :
We present a new one-transistor hybrid nonvolatile memory based on the combination of two distinctive mechanisms, namely, remanent polarization in ferroelectrics and charge injection into floating nodes. The gate stack design and the memory operation of the hybrid device are aimed to offer mutually complementing benefits between the two mechanisms, thereby presenting superior performance over conventional ferroelectric (FE) FET and gate injection-based Flash memory. During program operation, a high negative bias at the gate orients the ferroelectric polarization to the applied field. In addition, electrons at the gate electrode also tunnel into the floating nodes located between the ferroelectric thin film and the thin top tunnel dielectric and increase the total memory window. High electric displacement in the ferroelectric enables field enhancement in the tunnel dielectric for faster program and erase operations. During retention, the injected electrons reduce the depolarization field in the ferroelectrics, and the remanent polarization reduces the electric field in the tunnel oxide, which helps in the longer retention of the programmed state by the two additive memory mechanisms. Part I evaluates the benefits of the hybrid gate stack through 1-D simulations incorporating the polarization-field (P-E) hysteresis in the ferroelectric layer. The simulations provide a guideline for optimal gate stack design of the proposed hybrid memory. The following Part II then discusses the fabrication and experimental validation.
Keywords :
charge injection; electric fields; ferroelectric storage; ferroelectric thin films; field effect memory circuits; flash memories; random-access storage; semiconductor device models; tunnelling; 1D simulation; P-E hysteresis; additive memory mechanisms; charge hybrid nonvolatile memory; charge injection; depolarization field reduction; device concept; device modeling; electric displacement; electric field reduction; electron tunnelling; ferroelectric layer; ferroelectric polarization; ferroelectric thin film; field enhancement; floating nodes; gate electrode; gate stack design; hybrid gate stack; one-transistor hybrid nonvolatile memory; polarization-field hysteresis; remanent polarization; thin top tunnel dielectric; tunnel oxide; Dielectrics; Ferroelectric materials; Geometry; Hysteresis; Iron; Logic gates; Materials; Charge trap; Flash; ferroelectric (FE); hybrid; nonvolatile memory;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2011.2175396
Filename :
6096400
Link To Document :
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