DocumentCode
1391486
Title
Via assignment in single-row routing
Author
Bhasker, Jayaram ; Sahni, Sartaj
Author_Institution
AT&T Bell Labs., Middletown, PA, USA
Volume
38
Issue
1
fYear
1989
fDate
1/1/1989 12:00:00 AM
Firstpage
142
Lastpage
148
Abstract
Examines the via assignment problem that arises when the single-row routing approach to the interconnection problem is used. Some new complexity results and two new heuristics are obtained. Experimental results establish the superiority of the new heuristics over earlier ones
Keywords
circuit layout CAD; computational complexity; printed circuit design; complexity results; heuristics; interconnection; multilayer PCB; single-row routing; via assignment; Computer science; Integrated circuit interconnections; Minimization; Nonhomogeneous media; Pins; Polynomials; Printed circuits; Routing;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.8737
Filename
8737
Link To Document