DocumentCode
1391783
Title
High-gain emitter inversion layer PNP vertical bipolar transistor in compensated CMOS technology
Author
Jankovic, N.D.
Author_Institution
Fac. of Electron. Eng., Nis Univ., Serbia
Volume
34
Issue
10
fYear
1998
fDate
5/14/1998 12:00:00 AM
Firstpage
984
Lastpage
985
Abstract
To improve the value of β of a pnp-merged vertical bipolar transistor (VET) in `pseudo-BiCMOS´ technology, a novel VBT design with an inversion layer-extended emitter is proposed. A high emitter injection efficiency of the forward-biased inversion layer is demonstrated in a pnp VET fabricated in 1 μm compensated CMOS technology
Keywords
BiCMOS integrated circuits; bipolar transistors; integrated circuit design; inversion layers; PNP vertical bipolar transistor; VBT; compensated CMOS technology; emitter injection efficiency; emitter inversion layer; forward-biased inversion layer; pseudo-BiCMOS technology;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19980732
Filename
682969
Link To Document