• DocumentCode
    1391921
  • Title

    Design for testability for future digital avionics systems

  • Author

    Subramanyam, V.R. ; Stine, L.R.

  • Author_Institution
    TRW, San Diego, CA, USA
  • Volume
    3
  • Issue
    6
  • fYear
    1988
  • fDate
    6/1/1988 12:00:00 AM
  • Firstpage
    2
  • Lastpage
    6
  • Abstract
    The authors describe an integrated testing approach called the Maintenance and Diagnostic System (MADS), which was developed for digital avionics systems using VHSIC and semicustom devices. Mission/operational requirements dictate high availability with capability to detect 98% of all faults and isolate 90% of these faults to a line replacement module (LRM) or 95% of the faults to two LRMs. MADS achieves these goals by defining a module maintenance node (MMN) chip set for each LRM in the system and the design for testability concepts for hardware. The MMN aids parallel, high-speed testing of LRMs, isolating the fault(s) to a module/chip level while incurring less than 10% overhead. It uses the concepts of scan set design, pseudorandom test vector generation, output response compression, and separate scan set loops to test the SSI-MSI logic on the LRM. It also stores interim test results and run-time fault information to isolate the hard-to-reproduce failures and performs verification of interchip and intermodule wiring.<>
  • Keywords
    aircraft instrumentation; digital instrumentation; fault location; integrated circuit testing; logic testing; maintenance engineering; IC testing; Maintenance and Diagnostic System; SSI-MSI logic; VHSIC; availability; design for testability; digital avionics; fault location; hard-to-reproduce failures; high-speed testing; integrated testing; interchip wiring; intermodule wiring; line replacement module; logic testing; module maintenance node; output response compression; parallel testing; pseudorandom test vector generation; semicustom devices; separate scan set loops; verification; Aerospace electronics; Availability; Design for testability; Fault detection; Hardware; Logic design; Logic testing; Runtime; System testing; Very high speed integrated circuits;
  • fLanguage
    English
  • Journal_Title
    Aerospace and Electronic Systems Magazine, IEEE
  • Publisher
    ieee
  • ISSN
    0885-8985
  • Type

    jour

  • DOI
    10.1109/62.874
  • Filename
    874