DocumentCode
1392260
Title
An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise
Author
Chiu, Tang-Jung ; Gong, Jeng ; King, Ya-Chin ; Lu, Chih-Cheng ; Chen, Hsin
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
32
Issue
1
fYear
2011
Firstpage
9
Lastpage
11
Abstract
As the low-frequency noise of a transistor grows nonnegligible in advanced technologies, the possibility of using noise for computation is becoming an alternative, receiving more and more attention. The ability to control the noise level would further enrich the flexibility of the circuit design. Therefore, this letter presents a dual-gate field-effect transistor in an octagonal shape. By changing the voltage of an extra gate above the shallow trench isolation, the transistor is able to adapt its low-frequency noise over several decades and in a power-efficient manner. The octagonal geometry further makes sufficient a voltage range from 0 to 5 V for the noise adaptation. Moreover, the transistor is fabricated with the standard CMOS logic process without additional masks. All the features underpin the development of large-scale noisy computation in integrated circuits.
Keywords
CMOS logic circuits; field effect transistors; geometry; CMOS logic process; dual-gate field-effect transistor; low-frequency noise; octagonal dual-gate transistor; octagonal geometry; Geometry; Logic gates; Low-frequency noise; Noise level; Noise measurement; Transistors; Dual-gate transistor; low-frequency noise; noise adaptability; shallow trench isolation (STI);
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2010.2089491
Filename
5654532
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