• DocumentCode
    1392921
  • Title

    FISH: Fast Instruction SyntHesis for Custom Processors

  • Author

    Atasu, Kubilay ; Luk, Wayne ; Mencer, Oskar ; Özturan, Can ; Dündar, Günhan

  • Author_Institution
    IBM Res. - Zurich, Rüschlikon, Switzerland
  • Volume
    20
  • Issue
    1
  • fYear
    2012
  • Firstpage
    52
  • Lastpage
    65
  • Abstract
    This paper presents Fast Instruction SyntHesis (FISH), a system that supports automatic generation of custom instruction processors from high-level application descriptions to enable fast design space exploration. FISH is based on novel methods for automatically adapting the instruction set to match an application in a high-level language such as C or C++. FISH identifies custom instruction candidates using two approaches: 1) by enumerating maximal convex subgraphs of application data flow graphs and 2) by integer linear programming (ILP). The experiments, involving ten multimedia and cryptography benchmarks, show that our contributed algorithms are the fastest among the state-of-the-art techniques. In most cases, enumeration takes only milliseconds to execute. The longest enumeration run-time observed is less than six seconds. ILP is usually slower than enumeration, but provides us with a complementary solution technique. Both enumeration and ILP allow the use of multiple different merit functions in the evaluation of data-flow subgraphs. The experiments demonstrate that, using only modest additional hardware resources, up to 30-fold performance improvement can be obtained with respect to a single-issue base processor.
  • Keywords
    electronic design automation; system-on-chip; FISH; automatic generation; cryptography benchmarks; custom processors; data flow subgraphs; fast instruction synthesis; high level language; multimedia; state of the art techniques; Clustering algorithms; Complexity theory; Marine animals; Program processors; Registers; System-on-a-chip; Upper bound; Custom processors; design automation; design optimization; graph theory; mathematical programming; subgraph enumeration; system-on-chip (SoC);
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2010.2090543
  • Filename
    5654626