Efficient implementation of a planar clock routing with the treatment of obstacles

Author

Kim, Haksu ; Zhou, Dian

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina Univ., Charlotte, NC, USA

Volume

19

Issue

10

fYear

2000

fDate

10/1/2000 12:00:00 AM

Firstpage

1220

Lastpage

1225

Abstract

This paper presents a set of techniques for developing a planar clock routing with the treatment of obstacles in high speed VLSI design. The planar clock routing framework has two key components. The first component employs a cutting-line embedding (CLE) routine algorithm to construct a planar clock tree topology. The routing constructed by CLE contains crossings over the obstacles in the presence of obstacles. Thus, the second component is a planar obstacle-avoiding (POA) routing scheme to clean up those crossings. These two schemes together give a good enhancement in convenient usage and performance to build a planar clock routing

Keywords

VLSI; application specific integrated circuits; circuit layout CAD; clocks; high-speed integrated circuits; integrated circuit design; logic CAD; network routing; network topology; clock tree topology; cutting-line embedding; high speed VLSI design; planar clock routing; planar obstacle-avoiding routing scheme; Chip scale packaging; Circuit simulation; Clocks; Design automation; Electrothermal effects; Integrated circuit modeling; Routing; Temperature; Timing; US Department of Transportation;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.875342

Filename

875342