Cycle-slipping probability of first-order phase-locked loop using transient analysis

The first-order phase-locked loop is a standard feedback device commonly used to provide both carrier and clock synchronisation in digital transmission systems. At low signal-to-noise ratios increased jitter on the timing estimates results in a raised probability of symbol error and an increased likelihood of synchroniser symbol slips; in the latter case, symbols are either deleted from or inserted into the received data stream. The paper re-examines the full transient modulo-2π and nonmodulo-2π phase error process and demonstrates that the probability of cycle-slipping with time can be expressed in terms of the loop cycle-slipping frequency as determined from a previous stationary analysis of the loop