• DocumentCode
    1393550
  • Title

    Decoupled sectored caches

  • Author

    Seznec, André

  • Author_Institution
    IRISA, Rennes, France
  • Volume
    46
  • Issue
    2
  • fYear
    1997
  • fDate
    2/1/1997 12:00:00 AM
  • Firstpage
    210
  • Lastpage
    215
  • Abstract
    Maintaining a low tag array size is a major issue in many cache designs. In the decoupled sectored cache, we present in this paper, the monolithic association between a cache block and a tag location is broken; the address tag location associated with a cache line location is dynamically chosen at fetch time among several possible locations. The hit ratio for a decoupled sectored cache is very close to the hit ratio for a nonsectored cache. Then a decoupled sectored cache will allow the same level of performance as a nonsectored cache, but at a significantly lower hardware cost
  • Keywords
    cache storage; memory architecture; address tag location; cache designs; cache line location; decoupled sectored caches; low tag array size; monolithic association; tag location; Automatic control; Costs; Hardware; Information retrieval; Logic arrays; Logic design; Microprocessors; Read-write memory;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.565601
  • Filename
    565601