• DocumentCode
    1393719
  • Title

    Statistical power estimation of CMOS logic circuits with variable errors

  • Author

    Park, Y.H. ; Park, E.S.

  • Author_Institution
    Electron. & Telecommun. Res. Inst., Taejon, South Korea
  • Volume
    34
  • Issue
    11
  • fYear
    1998
  • fDate
    5/28/1998 12:00:00 AM
  • Firstpage
    1054
  • Lastpage
    1056
  • Abstract
    A statistical power estimation method is proposed where estimation time and accuracy can be balanced by assigning smaller (higher) errors to the nodes with higher (lower) power dissipation. To determine the errors, a quadratic programming based problem is formulated. Experimental results show a drastic reduction in the number of simulation patterns compared to previous methods
  • Keywords
    CMOS logic circuits; CMOS logic circuits; estimation accuracy; estimation time; power dissipation; quadratic programming based problem; statistical power estimation; variable errors;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980801
  • Filename
    683786
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1393719