Title :
Statistical power estimation of CMOS logic circuits with variable errors
Author :
Park, Y.H. ; Park, E.S.
Author_Institution :
Electron. & Telecommun. Res. Inst., Taejon, South Korea
fDate :
5/28/1998 12:00:00 AM
Abstract :
A statistical power estimation method is proposed where estimation time and accuracy can be balanced by assigning smaller (higher) errors to the nodes with higher (lower) power dissipation. To determine the errors, a quadratic programming based problem is formulated. Experimental results show a drastic reduction in the number of simulation patterns compared to previous methods
Keywords :
CMOS logic circuits; CMOS logic circuits; estimation accuracy; estimation time; power dissipation; quadratic programming based problem; statistical power estimation; variable errors;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980801
