IBM RISC System/6000: architecture and performance

Author

Oehler, Richard R. ; Blasgen, Michael W.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

11

Issue

3

fYear

1991

fDate

6/1/1991 12:00:00 AM

Firstpage

14

Lastpage

17

Abstract

The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given.<>

Keywords

IBM computers; microprocessor chips; parallel architectures; performance evaluation; reduced instruction set computing; IBM RISC System/6000; architecture; branch; cache management; fixed-point; floating-point; instruction set; performance; superscalar; superscalar microprocessor; CMOS technology; Computer aided instruction; Computer architecture; High performance computing; Microprocessors; Parallel processing; Pipelines; Reduced instruction set computing; Scheduling; Tiles;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.87565

Filename

87565