Title :
CMOS dynamic ternary circuit with full logic swing and zero-static power consumption
Author :
Toto, F. ; Saletti, R.
Author_Institution :
Dipt. di Ingegneria dell´´Inf. Elettronica Inf. Telecommun., Pisa Univ., Italy
fDate :
5/28/1998 12:00:00 AM
Abstract :
A new dynamic circuit scheme to realise ternary logic is presented. The main properties are the use of the standard CMOS process without any modification of the thresholds, the minimum possible number of external voltage levels (three), the highest possible logic swing and noise margins and the absence of static power consumption
Keywords :
CMOS logic circuits; logic design; logic gates; multivalued logic circuits; ternary logic; CMOS dynamic ternary circuit; full logic swing; noise margins; standard CMOS process; ternary inverter; ternary logic; zero-static power consumption;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980754
