A reliable profiled lightly doped drain (PLD) cell for high-density submicrometer EPROM´s and flash EEPROM´s

Author

Yoshikawa, Kuniyoshi ; Sato, Masaki ; Ohshima, Yoichi

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

37

Issue

4

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

999

Lastpage

1006

Abstract

A cell with a profiled lightly doped drain (PLD) structure is proposed for realizing high-density nonvolatile memories in the submicrometer range. The PLD cell has a surface n^- layer with a diffusion self-aligned (DSA) boron layer, in addition to a deep phosphorus n^- layer. This structure enhances hot-electron generation during write and significantly reduces it during read. The cell exhibits improved data retention as a result of reduced band-to-band tunneling leakage current. The optimized PLD cell combines improved soft-write immunity with high read current, and low gate-induced breakdown leakage with high-speed writing. Simulation results and measurements on a fabricated test structure confirm these characteristics

Keywords

CMOS integrated circuits; EPROM; circuit reliability; hot carriers; integrated memory circuits; leakage currents; Si:B-Si:P; band-to-band tunneling leakage current; data retention; diffusion self-aligned layer; flash EEPROM; gate-induced breakdown leakage; high read current; high-density nonvolatile memories; high-speed writing; hot-electron generation; n-well CMOS process; profiled lightly doped drain cell; reliability; soft-write immunity; submicrometre EPROM; surface n^- layer; Boron; EPROM; Electric breakdown; Hot carriers; Leakage current; Nonvolatile memory; Read-write memory; Testing; Tunneling; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.52435

Filename

52435