Muon-Induced Single Event Upsets in Deep-Submicron Technology

Author

Sierawski, Brian D. ; Mendenhall, Marcus H. ; Reed, Robert A. ; Clemens, Michael A. ; Weller, Robert A. ; Schrimpf, Ronald D. ; Blackmore, Ewart W. ; Trinczek, Michael ; Hitti, Bassam ; Pellish, Jonathan A. ; Baumann, Robert C. ; Wen, Shi-Jie ; Wong, Rick

Author_Institution

Inst. for Space & Defense Electron., Vanderbilt Univ., Nashville, TN, USA

Volume

57

Issue

6

fYear

2010

Firstpage

3273

Lastpage

3278

Abstract

Experimental data are presented that show low-energy muons are able to cause single event upsets in 65 nm, 45 nm, and 40 nm CMOS SRAMs. Energy deposition measurements using a surface barrier detector are presented to characterize the kinetic energy spectra produced by the M20B surface muon beam at TRIUMF. A Geant4 application is used to simulate the beam and estimate the energy spectra incident on the memories. Results indicate that the sensitivity to this mechanism will increase for scaled technologies.

Keywords

CMOS memory circuits; Monte Carlo methods; SRAM chips; muons; radiation effects; CMOS SRAMs; Geant4 application; M20B surface muon beam; Monte Carlo method; SEU; TRIUMF; deep-submicron technology; energy deposition measurements; energy spectra incident; kinetic energy spectra; low-energy muons; muon-induced single event upsets; static random access memory; surface barrier detector; terrestrial ionizing radiation; Ionization; Mesons; Monte Carlo methods; SRAM chips; Single event upset; Direct ionization; Geant4; Monte Carlo; muons; single event upset (SEU); static random access memory (SRAM);

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2010.2080689

Filename

5658005