2.488 Gb/s SONET multiplexer/demultiplexer with frame detection capability

Author

Kong, Dennis T.

Author_Institution

Bellcore, Red Bank, NJ, USA

Volume

9

Issue

5

fYear

1991

fDate

6/1/1991 12:00:00 AM

Firstpage

726

Lastpage

731

Abstract

The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer´s performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1×10^-14. Both ICs were tested at data rates up to 3 Gb/s

Keywords

field effect integrated circuits; multiplexing equipment; optical communication equipment; 2.488 Gbit/s; GaAs; MESFET technology; SONET multiplexer/demultiplexer; bit error rate; byte aligner; demultiplexer; frame detection capability; integrated circuit; Bit error rate; Demultiplexing; Gallium arsenide; Integrated circuit technology; MESFET integrated circuits; Multiplexing; Prototypes; SONET; Signal design; Testing;

fLanguage

English

Journal_Title

Selected Areas in Communications, IEEE Journal on

Publisher

ieee

ISSN

0733-8716

Type

jour

DOI

10.1109/49.87642

Filename

87642