Title :
Contribution of Control Logic Upsets and Multi-Node Charge Collection to Flip-Flop SEU Cross-Section in 40-nm CMOS
Author :
Narasimham, Balaji ; Wang, Jung K. ; Buer, Myron ; Gorti, Ramamurthy ; Chandrasekharan, Karthik ; Warren, Kevin M. ; Sierawski, Brian D. ; Schrimpf, Ronald D. ; Reed, Robert A. ; Weller, Robert A.
Author_Institution :
Broadcom Corp., Irvine, CA, USA
Abstract :
Heavy-ion measurements on 40-nm flip-flops indicate pattern dependence of cross-section resulting from local control logic upsets, such as clock nodes. A Monte-Carlo model of the flip-flop, calibrated to the heavy-ion data, is used to analyze the impact of multi-node charge collection within a flip-flop due to a single particle strike. Depending on the nodes that collect charge, multi-node charge collection can either increase or decrease the vulnerability of the cell. For neutrons, the overall effect of such events was found to be a net increase in cross-section by up to 16%.
Keywords :
CMOS logic circuits; Monte Carlo methods; flip-flops; Monte-Carlo model; clock nodes; control logic upsets; flip-flop SEU cross-section; heavy-ion data; heavy-ion measurements; local control logic; multinode charge collection; single particle strike; single-event upset; CMOS technology; Flip-flops; Monte Carlo methods; Single event upset; Cross-section; MRED; Monte-Carlo; flip-flop; heavy-ion; multi-node charge collection; single-event upset; soft error;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2010.2081687